Animations for

Computer Organization and Architecture, Ninth Edition

by William Stallings

Chapter 4 - Cache Memory

Cache Simulator: Emulates small sized caches based on a user-input cache model and displays the cache contents at the end of the simulation cycle based on an input sequence which is entered by the user, or randomly generated if so selected.
Cache Time Analysis: Demonstrates Average Memory Access Time analysis for the cache parameters you specify.
Multitask Cache Demonstrator: Models cache on a system that supports multitasking.
Selective Victim Cache Simulator: Compares three different cache policies.

Chapter 5 - Internal Memory

Interleaved Memory Simulator: Demonstrates the effect of interleaving memory.

Chapter 6 - External Memory

RAID: Determine storage efficiency and reliability.

Chapter 7 - Input/Output

I/O System Design Tool: Evaluates comparative cost and performance of different I/O systems.

Chapter 8 - OS Support

Page Replacement Algorithms: Compares LRU, FIFO, and Optimal.
More Page Replacement Algorithms: Compares a number of policies.

Chapter 14 - CPU Structure and Function

Reservation Table Analyzer: A reservation table is a way of representing the task flow pattern of a pipelined system.
Branch Prediction: Demonstrates three different branch prediction schemes.
Branch Target Buffer: Combined branch predictor/branch target buffer simulator.

Chapter 15 - Reduced Instruction Set Computers

MIPS 5-Stage Pipeline: Simulates the pipeline.
Loop unrolling: A software technique for exploiting instruction-level parallelism.

Chapter 16 - Instruction-Level Parallelism and Superscalar Processors

Pipeline with static vs. dynamic scheduling: A more complex simulation of the MIPS pipeline.
Reorder Buffer Simulator: Simulates instruction reordering in a RISC pipeline.
Scoreboarding technique for dynamic scheduling: Simulation of an instruction scheduling technique used in a number of processors.
Tomasulo's Algorithm: Simulation of another instruction scheduling technique.
Alternative Simulation of Tomasulo's Algorithm: Simulation of another instruction scheduling technique.

Chapter 17 - Parallel Processing

Vector Processor Simulation: Demonstrates execution of vector processing instructions.

These animations were developed at the University of Massachusetts under the supervision of Professor Israel Koren.