Cache Simulator: Emulates small sized caches based on a user-input cache model and displays the cache contents at the end of the simulation cycle based on an input sequence which is entered by the user, or randomly generated if so selected.
Cache Time Analysis: Demonstrates Average Memory Access Time analysis for the cache parameters you specify.
Multitask Cache Demonstrator: Models cache on a system that supports multitasking.
Selective Victim Cache Simulator: Compares three different cache policies.
Interleaved Memory Simulator: Demonstrates the effect of interleaving memory.
RAID: Determine storage efficiency and reliability.
I/O System Design Tool: Evaluates comparative cost and performance of different I/O systems.
Page Replacement Algorithms: Compares LRU, FIFO, and Optimal.
More Page Replacement Algorithms: Compares a number of policies.
Reservation Table Analyzer: A reservation table is a way of representing the task flow pattern of a pipelined system.
Branch Prediction: Demonstrates three different branch prediction schemes.
Branch Target Buffer: Combined branch predictor/branch target buffer simulator.
MIPS 5-Stage Pipeline: Simulates the pipeline.
Loop unrolling: A software technique for exploiting instruction-level parallelism.
Pipeline with static vs. dynamic scheduling: A more complex simulation of the MIPS pipeline.
Reorder Buffer Simulator: Simulates instruction reordering in a RISC pipeline.
Scoreboarding technique for dynamic scheduling: Simulation of an instruction scheduling technique used in a number of processors.
Tomasulo's Algorithm: Simulation of another instruction scheduling technique.
Alternative Simulation of Tomasulo's Algorithm: Simulation of another instruction scheduling technique.
Vector Processor Simulation: Demonstrates execution of vector processing instructions.
These animations were developed at the University of Massachusetts under the supervision of Professor Israel Koren.